An integrated circuit memory is generally implemented as an array of memory cells in a plurality of rows and columns. Memory cells are addressable through row and column decoders. Data is then written into, or read from, the addressed memory cells. Also, an integrated circuit memory may be subdivided into blocks of memory cells which are addressed by block decoding. A plurality of blocks may be grouped into arrays of blocks with a memory containing one or more arrays.
As the memory storage capacity of integrated circuit memories increases, the possibility of having manufacturing defects in the rows and columns increases. And this results in a decrease in production yields. One way to increase production yields in large integrated circuit memories is column and row redundancy. In an integrated circuit memory with redundancy, a manufacturing defect in a particular row can be cured by using a redundant row in place of the defective row. Likewise, a defect in a particular column can be cured by using a redundant column to replace the defective column. To implement column and row redundancy, redundant control logic and redundant read/write data paths are also required.
In order to repair a defective row or column, the defective row or column is deselected and a redundant row or column is assigned in its place by blowing a fusible link. The fusible link may be blown using a high-energy laser, or may be blown electrically at probe test. The ability to repair a memory that has only a few defective rows or columns can result in substantially increased manufacturing yields.
Some integrated circuit memories which use a technique known as the revolutionary pinout has input/output circuitry on both sides of the array of the memory cells allowing for shorter data paths and faster access times. Also, integrated circuit memories using the revolutionary pinout technique have power and ground pins on the sides of the package, whereas integrated circuit memories using the conventional pinout technique have power and ground pins on the corners. A problem that has arisen with redundancy in memories that use the revolutionary pinout is that the access time of the redundant memory array may be slower than the access time of the main memory. This is because the redundant read/write control logic is centralized, thus requiring global redundant control signals to travel longer distances to reach the separated input/output circuitry. This problem becomes worse as the number of memory cells on an integrated circuit memory becomes very large.
Another problem associated with redundancy is increased die width due to the redundant read/write control signals crossing the array area. In order for the die to fit into the standard SOJ/FLAT package, the die width must not exceed a maximum value. Thus the die width of larger memories may become a critical factor.